BEM employing Taylor expansion for modelling complex PCB layout

A method for extending an existing quasi-static BEM electromagnetic solver to extremely large problems has been presented in outline. The method uses low order Taylor series expansions for the fields, and this allows a reduction in the memory required for compression of the equivalent circuit generated from order N² to order N, where N is the number of boundary elements into which the conductor surfaces are sub-divided. The complete analysis separates into distinct inductance and capacitance problems. The new extension to the method has been prototyped successfully using a very large, but otherwise simple capacitance problem. However, it may still be concluded that the method will be effective and accurate for real applications. Circuit compression had previously been shown to reduce the CPU requirement by orders of magnitude without significant loss of accuracy. The extension described here greatly reduces the memory required for this compression when the problem is very large, but at some cost in speed