ASIC replacement for an SSI component design-a case study

This case study covers the practical issues of design for functionality, design for simulation, and design for testability in replacing aging SSI (small-scale-integration) component designs with ASIC (application-specific integrated circuit) gate arrays. The replacement of a 169-TTL (transistor-transistor logic) component design with a CMOS ASIC gate array is presented. Existing functionality is maintained through a series of ordered conversion steps that minimize the probability of error in the conversion. Design modifications, such as the addition of initialization circuitry, were necessary to take advantage of CAE simulation tools. The faster ASIC technology coupled with design modifications allowed the time-to-simulate to be decreased by a factor of 10000. A unique pseudorandom number generation signature analysis technique is presented that interrogates highly sequential designs. The testability scheme and other design techniques improved stuck-at fault coverage by more than 640%. The economic advantages, knowledge gained, and tools developed that are applicable to future design work are discussed