DocumentCode
2083559
Title
Simulation based verification of register-transfer level behavioral synthesis tools
Author
Ernst, R. ; Sutarwala, S. ; Jou, J.-Y. ; Tong, M.
Author_Institution
Inst. fur Datenverarbeitungsanlagen, Tech. Univ. Braunschweig, Germany
fYear
1990
fDate
12-15 Mar 1990
Firstpage
396
Lastpage
400
Abstract
The authors present a simulation based system for verification of register-transfer level behavioral synthesis tools. Applications are tool debugging and automatic regression test. Key feature is a transformation of sequential circuits for application of pseudo-random test patterns. The results show a high relevance of verification with pseudo-random patterns
Keywords
circuit analysis computing; logic testing; automatic regression test; pseudo-random test patterns; register-transfer level behavioral synthesis tools; sequential circuits; simulation based verification; tool debugging; Automatic testing; Circuit simulation; Circuit synthesis; Circuit testing; Debugging; Formal verification; Hardware; Sequential analysis; Sequential circuits; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location
Glasgow
Print_ISBN
0-8186-2024-2
Type
conf
DOI
10.1109/EDAC.1990.136680
Filename
136680
Link To Document