Title :
A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI
Author :
Wu, Chung-Yu ; Ker, Ming-Dou ; Lee, Chung-Yuan ; Ko, Joe ; Lin, Larry
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Abstract :
A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structure is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown
Keywords :
CMOS integrated circuits; VLSI; electrostatic discharge; thyristors; CMOS VLSI; dual parasitic SCR structures; failure thresholds; human-body-mode; junction breakdown; machine-mode; negative ESD protection; on-chip ESD protection circuit; positive ESD protection; triggering voltages; Breakdown voltage; Circuit testing; Electrostatic discharge; Industrial electronics; Low voltage; Protection; Pulse circuits; Threshold voltage; Thyristors; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164085
