DocumentCode
2083674
Title
Incremental netlist compilation for IKOS hardware logic simulator
Author
Wang, Kai ; Chen, Jerry
Author_Institution
IKOS Syst. Inc., Sunnyvale, CA, USA
fYear
1989
fDate
25-28 Sep 1989
Lastpage
38047
Abstract
Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be reproduced and can be loaded to the simulator for the times of occurrences by adjusting for the base offsets
Keywords
circuit analysis computing; logic CAD; IKOS hardware logic simulator; hierarchical network patterns; Artificial intelligence; Data structures; Hardware; Joining processes; Logic design; Partitioning algorithms; Pins; Signal design; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1989.123223
Filename
123223
Link To Document