A new switch-level test pattern generation algorithm based on single path over a graph representation

Author

Ferrer, C. ; Oliver, J. ; Valderrama, E.

Author_Institution

Centre Nacional de Microelectronica, Univ. Autonoma de Barcelona, Bellaterra, Spain

fYear

1990

fDate

12-15 Mar 1990

Firstpage

402

Lastpage

406

Abstract

A new switch-level automatic test pattern generation algorithm for CMOS combinational network is presented. Such a generator can be applied to static and dynamic CMOS logics, and pseudo-NMOS ones. The fault model includes stuck-on and stuck-open transistor faults, although the algorithm can be easily generalized to open and short faults. The algorithm follows a PODEM-like strategy, and may be directly applied to a wide spread of CMOS logics. Test vector generation times have been notoriously improved, comparing with other switch-level algorithms

Keywords

CMOS integrated circuits; combinatorial circuits; integrated logic circuits; logic testing; CMOS combinational network; PODEM-like strategy; dynamic CMOS logics; fault model; graph representation; pseudo-NMOS; single path; static CMOS logics; stuck-on; stuck-open; switch-level test pattern generation algorithm; Automatic test pattern generation; Automatic testing; CMOS logic circuits; Circuit faults; Circuit testing; Integrated circuit interconnections; Semiconductor device modeling; Switching circuits; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990., EDAC. Proceedings of the European

Conference_Location

Glasgow

Print_ISBN

0-8186-2024-2

Type

conf

DOI

10.1109/EDAC.1990.136681

Filename

136681