Self controllable voltage level (SVL) for low power consumption

A large portion of the on chip power is consumed by clock distribution network and flip flops. Various Design techniques are used for a low power clocking system. Among them is an effective way to reduce capacity of clock load by minimizing number of clocked transistors, conditional data mapping Flip-flop (CDMFF), Novel clocked pair shared Flip-Flop (CPSFF) and SVL-5TTSPC which reduces the number of local clocked transistors by approximately 40%. In order to achieve a high performance and power efficiency, a self controllable voltage level circuit is used in the proposed method.