Fault modelling and fault equivalence in CMOS technology

Author

Flotted, M.L. ; Landrault, C. ; Pravossoudovitch, S.

Author_Institution

Lab. d´´Automatique et de Microelectronique, Univ. de Montpellier II, Sci. et Tech. du Languedoc, France

fYear

1990

fDate

12-15 Mar 1990

Firstpage

407

Lastpage

412

Abstract

The need of greater confidence for fault coverage of test sequences for VLSI circuits has led to the proposal of more accurate fault models and test pattern generation tools. Such improvement induces a large increase in fault list to be considered and CPU time to generate test. The authors propose a complete methodology to obtain a minimal set of faults. This methodology is based upon theoretical basis allowing the determination of the equivalence and dominance of non-classical CMOS faults

Keywords

CMOS integrated circuits; automatic testing; circuit analysis computing; fault location; integrated circuit testing; CMOS technology; VLSI; dominance; equivalence; fault coverage; fault equivalence; fault modelling; nonclassical CMOS faults; test pattern generation tools; Automatic testing; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Integrated circuit modeling; Proposals; Semiconductor device modeling; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990., EDAC. Proceedings of the European

Conference_Location

Glasgow

Print_ISBN

0-8186-2024-2

Type

conf

DOI

10.1109/EDAC.1990.136682

Filename

136682