A user-configurable RAM compiler for gate arrays

Author

Steinweg, Russell L. ; Zampaglione, Mike ; Lin, Pei

Author_Institution

VLSI Technol. Inc., San Jose, CA, USA

fYear

1989

fDate

25-28 Sep 1989

Lastpage

38047

Abstract

A flexible RAM compiler for gate arrays that is fully integrated into the user design tools is described. The various hardware and software features of the compiler are described, including variable aspect ratio with automatic selection, along with the design tool integration. The RAM compiled for minimum area came out with the 32 words in the core organized as 32 words down by one word across. It has a typical access time of about 10 ns. The RAM compiled for most square aspect ratio ended up with a core organization of 16 words down by 2 words across and an access time of about 8 ns. The RAM compiled for minimum access time has a core organization of 8 words down by 4 words across, and an access time of about 7 ns. If desired, other aspect ratio variations than those chosen automatically using the optimization criteria can be compiled by using the manual override option to specify the core organization directly

Keywords

application specific integrated circuits; cellular arrays; circuit layout CAD; logic CAD; logic arrays; random-access storage; 7 to 10 ns; ASIC design; CAD; access time; automatic selection; computer aided design; core organization; design tool integration; gate arrays; manual override option; optimization criteria; user-configurable RAM compiler; variable aspect ratio; Costs; Hardware; Prototypes; Random access memory; Read-write memory; Routing; Silicon compiler; Software prototyping; Software tools; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123239

Filename

123239