A strategy for testability enhancement at layout level

Integrated circuits (ICs) need to be designed for testability. This paper presents a strategy for testability enhancement, at the lower levels of the design, which is supported in hardware refinement and software improvement. Main areas of low-cost software improvement, for test preparation, are identified as logic extraction, test vector sequencing and the introduction of circuit knowledge in fault simulation. The strategy for hardware improvement is based on realistic fault list generation, fault hardness classification, and layout-level DFT (design for testability) rules derivation. A software package for test preparation is extensively used to identify the realistic faults in MOS digital ICs which are harder to detect, and to derive layout rules for hard fault avoidance. Simulation examples are presented, that ascertain the conclusions drawn in this work