VLSi architecture design for algebraic soft-decision Reed-Solomon decoding

Reed-Solomon (RS) codes have very broad applications in digital communication and storage systems. The recently developed algebraic soft-decision decoding (ASD) algorithms of RS codes have caught much attention. These algorithms can achieve substantial coding gain with polynomial complexity by incorporating the reliability information from the channel into an algebraic interpolation process. ASD algorithms have two major steps: the interpolation and factorization. This paper first gives a review of available algorithms that can be used for the implementation of these steps. Particularly, we focus on the Nielson´s and Lee-O´Sullivan algorithms for the interpolation and the Roth-Ruckenstein algorithm for the factorization. Then hardware implementation bottlenecks of these algorithms are outlined, and existing efforts on VLSI architecture design for these algorithms are discussed. In addition, implementation results and comparisons are provided.