Title :
Efficient on-chip interconnects using CMS scheme with variation tolerant
Author :
Uma, T. ; Nirmaladevi, K.
Author_Institution :
Dept. of ECE, Paavai Eng. Coll., Namakkal, India
Abstract :
Current Mode Signaling Scheme-Bias is one of the efficient schemes to achieve high-speed and low power communication over long On-Chip interconnects. In early days the repeaters and boosters circuits [4] are used to drive the on-chip interconnects. In this paper CMS scheme with various types of delay elements which is inserted in the circuit is used to analyze the performance in terms of power and tolerant variation. CMS scheme has an importance that it has a trade-off between speed and power as in[1]. In addition, the voltage swing on the line is reduced in our proposed scheme as in [2]. By the inserting a conventional buffer as delay element the improvement in energy/bit is 87% as in [1]. Further to improve the performance of the CMS-Bias the d-latch can be used as a delay element which consumes less power compared to buffer.
Keywords :
buffer circuits; flip-flops; multiprocessor interconnection networks; system-on-chip; CMS-Bias; SoC; booster circuit; buffer; current mode signaling scheme; d-latch; delay element; on-chip interconnect; power variation; repeater; system-on-chip; tolerant variation; CMS scheme; interconnects; process variation; signaling scheme and variation tolerant;
Conference_Titel :
Computational Intelligence & Computing Research (ICCIC), 2012 IEEE International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4673-1342-1
DOI :
10.1109/ICCIC.2012.6510253
