Title :
Predictive analysis of sensitivity to chip-routing parasitics
Author :
Melville, Robert ; Yiannoulos, Aris
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significant for the performance specification prescribed by the designer. The value attached to a parasitic is a quantitative estimate of how significant the parasitic is. This information is derived from a simulation of the circuit prior to layout. The list of most significant routing parasitics could be used to provide feedback to a human designer, direct an automatic layout tool, or guide a circuit extractor
Keywords :
circuit analysis computing; circuit layout CAD; integrated circuit technology; sensitivity analysis; CAD; SPICE file; automatic layout tool; chip-routing parasitics; circuit extractor guidance; computer aided analysis; interconnection parasitics; performance sensitivities; performance specification; predictive analysis; Admittance; Analog circuits; Analog integrated circuits; Circuit simulation; Design methodology; Integrated circuit interconnections; Integrated circuit noise; SPICE; Shunt (electrical); Voltage;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1989.123245
