A two-chip CMOS 64 b mainframe processor chipset

Author

Yamagishi, Mikio ; Koide, Kazuo ; Ishiyama, Akira ; Yamagiwa, Akira ; Hayashi, Takehisa ; Satou, Youichi

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1991

fDate

12-15 May 1991

Abstract

A two-chip processor chipset with a full set of mainframe instructions is presented. One chip decodes instructions and executes arithmetic and logic operations. The other chip controls a buffer storage (cache) and translates logical addresses into physical. A hybrid of four-stage and five-stage pipelines and an on-chip microcode storage are adopted to execute LD/ST (load/store) and most R-R (register-register) instructions in a single cycle. Six kinds of macro cells and a macro-oriented clock distribution system are used to obtain a machine cycle time of 18 ns (typical). The chips are fabricated using 0.8-μm CMOS triple-metal layer technology and are each housed in a 400-pin PGA package

Keywords

CMOS integrated circuits; mainframes; microprocessor chips; packaging; 0.8 micron; 18 ns; 64 bit; 64 bit microprocessors; CMOS; PGA package; full set of mainframe instructions; machine cycle time; macro cells; macro-oriented clock distribution; mainframe processor chipset; on-chip microcode storage; triple-metal layer; two chip set; Arithmetic; Buffer storage; CMOS logic circuits; CMOS process; CMOS technology; Cache storage; Clocks; Decoding; Electronics packaging; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164093

Filename

164093