Title :
Simulation of on-chip interconnection effects in CMOS circuits
Author :
Piwowarska, Elzbieta
Author_Institution :
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
Abstract :
This paper describes shortly the methodology of postlayout VLSI chip verification oriented on interconnection parasitic effects. The method for selecting long and neighbouring interconnections is presented. Criteria for choosing the simulation models are described.
Keywords :
CMOS integrated circuits; VLSI; integrated circuit interconnections; integrated circuit modelling; CMOS circuit; VLSI chip; on-chip interconnection; parasitic effects; post-layout verification; simulation model; Attenuation; CMOS technology; Capacitance; Circuit simulation; Impedance; Inductance; Integrated circuit interconnections; RLC circuits; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
CAD Systems in Microelectronics, 2001. CADSM 2001. Proceedings of the 6th International Conference. The Experience of Designing and Application of
Conference_Location :
Lviv-Slavsko, Ukraine
Print_ISBN :
966-553-079-8
DOI :
10.1109/CADSM.2001.975827
