DocumentCode
2085946
Title
Simulation of on-chip interconnection effects in CMOS circuits
Author
Piwowarska, Elzbieta
Author_Institution
Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
fYear
2001
fDate
12-17 Feb. 2001
Firstpage
246
Lastpage
249
Abstract
This paper describes shortly the methodology of postlayout VLSI chip verification oriented on interconnection parasitic effects. The method for selecting long and neighbouring interconnections is presented. Criteria for choosing the simulation models are described.
Keywords
CMOS integrated circuits; VLSI; integrated circuit interconnections; integrated circuit modelling; CMOS circuit; VLSI chip; on-chip interconnection; parasitic effects; post-layout verification; simulation model; Attenuation; CMOS technology; Capacitance; Circuit simulation; Impedance; Inductance; Integrated circuit interconnections; RLC circuits; Semiconductor device modeling; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
CAD Systems in Microelectronics, 2001. CADSM 2001. Proceedings of the 6th International Conference. The Experience of Designing and Application of
Conference_Location
Lviv-Slavsko, Ukraine
Print_ISBN
966-553-079-8
Type
conf
DOI
10.1109/CADSM.2001.975827
Filename
975827
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