A fuzzy logic inference processor

Author

Fattaruso, John W. ; Mahant-Shetti, S.S. ; Barton, J. Brock

Author_Institution

Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1993

fDate

1-3 Dec 1993

Firstpage

210

Lastpage

214

Abstract

A mixed analog-digital fuzzy logic inference engine chip fabricated in an O.8 μm CMOS process is described. The interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules including a center-of-mass defuzzification, may be computed in 2 μsec

Keywords

CMOS integrated circuits; analogue processing circuits; fuzzy logic; inference mechanisms; microprocessor chips; mixed analogue-digital integrated circuits; 0.8 mum; 2 mus; O.8 μm CMOS process; analog charge-domain circuits; center-of-mass defuzzification; fuzzy logic inference processor; mixed analog-digital fuzzy logic inference engine chip; static RAM; Analog computers; Analog-digital conversion; CMOS process; Computer interfaces; Concurrent computing; Engines; Fuzzy logic; Logic arrays; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Fuzzy Control and Intelligent Systems, 1993., IFIS '93., Third International Conference on

Conference_Location

Houston, TX

Print_ISBN

0-7803-1485-9

Type

conf

DOI

10.1109/IFIS.1993.324186

Filename

324186