Comparative performance evaluation of power and area Network on Chip (NoC) architectures

Network on Chip (NoC) is rising as an efficient solution to solve the aggravating scalable interconnection architecture, designed in reality. The increasing quantity of cores that area unit integrated on a silicon die and, however the technology scaling has enabled designers to integrate many processors on a single chip realizing chip multi-processor (CMP). Problems arising from technology scaling have created power reduction, a very important design issue. Because the interconnection networks dissipate a significant portion of the total power budget, as interconnection network´s power efficiency and designing CMP are desirable. This paper provides comparative performance, area and power evaluation of the Network on Chip (NoC) proposals. The challenge to the efficiency of multi-core chips is that the energy functions communication with cores over a Network on Chip (NoC). If the several cores increase this energy, additionally will be increasing, imposing serious constraints on design and performance of each applications and architecture. Hence, the various design selections on Network on Chip (NoC) power consumption are critical to the achievement of the multi-core designs.