Title :
Proceedings: The Second Annual IEEE ASIC Seminar and Exhibit (Cat. No.89TH0280-8)
Abstract :
The following topics are dealt with: VLSI synthesis and layout compilation; design synthesis; logic synthesis; compilation for ASIC design; simulation and hardware acceleration; hardware description language compiler; data path; compilation for ASIC design; ASIC memories; design for testability test generation; high-performance systems; architecture core; signal processing ASIC; design and fault simulation; management and economics; cell libraries; analog design; and education. Abstracts of individual papers can be found under the relevant classification codes in this or other issues
Keywords :
VLSI; application specific integrated circuits; cellular arrays; circuit layout CAD; logic arrays; ASIC memories; VLSI synthesis; analog design; architecture core; cell libraries; compilation for ASIC design; data path; design for testability; design synthesis; economics; education; fault simulation; hardware acceleration; hardware description language compiler; high-performance systems; layout compilation; logic synthesis; management; signal processing ASIC; test generation;
Conference_Titel :
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location :
Rochester, NY, USA
DOI :
10.1109/ASIC.1989.123253
