• DocumentCode
    2086449
  • Title

    Sparse FIR filters and the impact on FPGA area usage

  • Author

    Patronis, Sean G. ; DeBrunner, Linda S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Florida State Univ., Tallahassee, FL
  • fYear
    2008
  • fDate
    26-29 Oct. 2008
  • Firstpage
    1862
  • Lastpage
    1866
  • Abstract
    In FIR filter design, a sparse filter is one that has a majority of zeros for coefficients. Generally, a sparse filter is designed in order to save area and speed up computations, but when implementing a sparse filter in an FPGA the expected area savings may not be realized. This paper shows that sparsity in an FIR filter does not generally translate directly into FPGA space (area) savings on a Virtex-4 FPGA.
  • Keywords
    FIR filters; field programmable gate arrays; FPGA area usage; field programmable gate arrays; sparse FIR filters; Application specific integrated circuits; Costs; Digital signal processing; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Frequency response; Production; Programmable logic arrays; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 2008 42nd Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA
  • ISSN
    1058-6393
  • Print_ISBN
    978-1-4244-2940-0
  • Electronic_ISBN
    1058-6393
  • Type

    conf

  • DOI
    10.1109/ACSSC.2008.5074751
  • Filename
    5074751
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2086449