Dynamically regularized RLS-DCD algorithm and its FPGA implementation

Author

Liu, Jie ; Zakharov, Yuriy

Author_Institution

Dept. of Electron., Univ. of York, York

fYear

2008

fDate

26-29 Oct. 2008

Firstpage

1876

Lastpage

1880

Abstract

In this paper, we present an FPGA implementation of a dynamically regularized recursive least squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. The proposed implementation allows significant increase in the weight update rate compared to a implementation based on unregularized QR decomposition; for 16 and 64-element adaptive antenna arrays, the update rate is as high as 176 kHz and 31 kHz, respectively.

Keywords

adaptive filters; field programmable gate arrays; least mean squares methods; FPGA; RLS-DCD algorithm; dichotomous coordinate descent iteration; recursive least squares adaptive filtering; Adaptive algorithm; Adaptive arrays; Adaptive filters; Equations; Field programmable gate arrays; Filtering algorithms; Heuristic algorithms; Least squares methods; Resonance light scattering; Robustness; Adaptive filter; DCD iterations; FPGA; RLS; antenna beamforming; dichotomous coordinate descent; regularization;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2008 42nd Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

978-1-4244-2940-0

Electronic_ISBN

1058-6393

Type

conf

DOI

10.1109/ACSSC.2008.5074754

Filename

5074754