Optimized Cu Pillar Bump flip chip package design for ultralow k device application

The demand for Cu Pillar Bump (CPB) has been significantly increased due to the fine pitch, high bandwidth, and high thermal performance requirement. However, the Cu pillar also has its own defect for the high peeling stress on the low K layer compare to the eutectic solder bump. To overcome the high peeling stress defect, optimize the CPB design is very important. This paper has three major topics using simulation results to analyze the silicon surface peeling stress. 1. The bump structure optimization, with the Cu pillar adhesion force on different material layers. 2. The solder joint condition impact. 3. The substrate material selection. Each topic has multiple design factors, with the CAE (Computer Aid Engineering) simulation result, the maximum silicon surface peeling stress point can be predicted, the bump and substrate structure can be optimized.