Title :
Pipelined implementation of AES encryption based on FPGA
Author :
Zhang, Yulin ; Wang, Xinggang
Author_Institution :
Sch. of Inf. Sci. & Eng., Univ. of Jinan, Jinan, China
Abstract :
This paper presents the outer-round only pipelined architecture for a FPGA implementation of the AES-128 encryption processor. The proposed design uses the Block RAM storing the S-box values and exploits two kinds of Block RAM. By combining the operations in a single round, we can reduce the critical delay. Therefore, our design can achieve a throughput of 34.7 Gbps at 271.15 Mhz and 2389 CLB Slices with 200 BRAM. We can get the much higher efficiency than any other implementation reported in the literature.
Keywords :
cryptography; field programmable gate arrays; multiprocessing systems; parallel architectures; pipeline processing; AES-128 encryption processor; FPGA; S-box values; block RAM storing; critical delay; pipelined architecture; pipelined implementation; Algorithm design and analysis; Computer architecture; Encryption; Field programmable gate arrays; Hardware; Random access memory; Throughput; AES; FPGA; efficiency; pipelined implementation;
Conference_Titel :
Information Theory and Information Security (ICITIS), 2010 IEEE International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-6942-0
DOI :
10.1109/ICITIS.2010.5688757
