A comparison of an ASIC synthesized design to a schematic entry design for a Viterbi decoder

A Viterbi decoder was designed by `hand´ and using synthesis. The Viterbi decoder was first created by hand using schematic capture and simulation tools. This same decoder architecture was then implemented by using a logic synthesis tool together with Verilog HDL. The size and speed of the decoders were compared as well as the time spent creating the two designs. Synthesis was easier, more efficient, and resulted in a design that is 13% faster and 16% smaller, primarily because synthesis could optimize larger circuits than possible by hand