DocumentCode
2087190
Title
Bounded Program Verification Using an SMT Solver: A Case Study
Author
Liu, Tianhai ; Nagel, Michael ; Taghdiri, Mana
Author_Institution
Karlsruhe Inst. of Technol., Karlsruhe, Germany
fYear
2012
fDate
17-21 April 2012
Firstpage
101
Lastpage
110
Abstract
We present a novel approach to bounded program verification that exploits recent advances of SMT solvers in modular checking of object-oriented code against its full specification. Bounded program verification techniques exhaustively check the specifications of a bounded program with respect to a bounded domain. To our knowledge, however, those techniques that target data-structure-rich programs reduce the problem to propositional logic directly, and use a SAT solver as the backend engine. Scalability, therefore, becomes a major issue due to bit blasting problems. In this paper, we present a novel approach that translates bounded Java programs and their JML specifications to quantified bit-vector formulas (QBVF) with arrays, and solves them using an SMT solver. QBVF allows logical constraints that are structurally closer to the original program and specification, and can be significantly simplified via high-level reasonings before being flattened in a basic logic. We also present a case study on a large-scale implementation of Dijkstra´s shortest path algorithm. The results indicate that our approach provides significant speedups over a SAT-based approach.
Keywords
Java; computability; constraint handling; formal specification; graph theory; object-oriented programming; program verification; Dijkstra shortest path algorithm; JML specification; QBVF; SAT solver; SAT-based approach; SMT solver; bounded Java program; bounded program verification; data-structure-rich program; high-level reasoning; logical constraint; modular checking; object-oriented code; program specification; propositional logic; quantified bit-vector formula; Arrays; Encoding; Indexes; Java; Null value; Reactive power; Resource management; Bounded verification; Dijkstra shortest path; JML; Quantified bit-vector; SMT; Scope-bounded checking;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Testing, Verification and Validation (ICST), 2012 IEEE Fifth International Conference on
Conference_Location
Montreal, QC
Print_ISBN
978-1-4577-1906-6
Type
conf
DOI
10.1109/ICST.2012.90
Filename
6200101
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