A 1.9 ns BiCMOS CAM macro with double match line architecture

Author

Nagamatsu, Tetsu ; Sakurai, Takayasu ; Hara, Hiroyuki ; Kobayashi, Shin´ichi ; Seta, Katsuhiro ; Noda, Makoto ; Uchida, Masanori ; Watanabe, Yoshinori ; Sano, Fumihiko

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1991

fDate

12-15 May 1991

Abstract

A 64-entry×32-b high-speed BiCMOS CAM (content addressable memory) macro is implemented on a 0.5 μm BiPNMOS sea-of-gates. In order to realize high-speed operation, a double match line (DML) architecture and a BiCMOS pull-up circuit are employed. The BiCMOS pull-up circuit imparts high drivability to a second match-line driver. A fabricated chip shows 1.9 ns of address-to-match delay time. The CAM macro also has high-density characteristics because a single CAM cell occupies only one basic cell of the gate array. Since the CAM macro is implemented on a gate array, the configuration can be altered easily and quickly depending on customers´ requests

Keywords

BIMOS integrated circuits; content-addressable storage; integrated memory circuits; memory architecture; 0.5 micron; 1.9 ns; BiCMOS CAM; BiPNMOS sea-of-gates; address-to-match delay time; double match line architecture; drivability; gate array; high-density characteristics; pull-up circuit; Added delay; BiCMOS integrated circuits; CADCAM; Computer aided manufacturing; Delay effects; Driver circuits; MOS devices; MOSFET circuits; Microelectronics; Semiconductor devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164102

Filename

164102