Title :
Rapid prototyping and performance evaluation of recoded multipliers using FPGAs
Author :
Saha, Arindam ; Krishnamurthy, Rangasayee
Author_Institution :
NSF/ERC for Comput. Field Simulations, Mississippi State Univ., MS, USA
Abstract :
High speed recoded parallel multipliers constitute an affordable improvement compared to the serial-parallel add-shift designs. We present in this paper, a detailed discussion of the development of these recoded multiplier algorithms and their FPGA implementations. The various issues involved in the design process are highlighted. The cost-performance comparison of the various recoded multipliers is studied and a discussion on the design methodology is also presented
Keywords :
digital arithmetic; logic arrays; parallel algorithms; performance evaluation; software prototyping; FPGAs; cost-performance comparison; design methodology; design process; performance evaluation; rapid prototyping; recoded multipliers algorithms; Algorithm design and analysis; Computational modeling; Design engineering; Design methodology; Design optimization; Field programmable gate arrays; Hardware; Logic arrays; Prototypes; Routing;
Conference_Titel :
Southeastcon '94. Creative Technology Transfer - A Global Affair., Proceedings of the 1994 IEEE
Conference_Location :
Miami, FL
Print_ISBN :
0-7803-1797-1
DOI :
10.1109/SECON.1994.324306
