Title :
Formal verification of timing conditions
Author :
Eveking, Hans ; Mai, Christoph
Author_Institution :
Inst. fur Datentech., Tech. Hochschule Darmstadt, Germany
Abstract :
Most timing-verifiers are analytical tools that determine, e.g., the delays on all paths, etc. This paper presents a completely different approach: timing-verification is performed by means of the formal transformation of CHDL descriptions. The principles of this procedure are presented and performance results of an implementation are given
Keywords :
circuit analysis computing; formal specification; theorem proving; CHDL descriptions; formal transformation; performance results; timing conditions; timing-verifiers; Assembly; Boolean algebra; Control systems; Delay; Formal verification; Hardware; Timing;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136701
