• DocumentCode
    2089359
  • Title

    Formal verification of timing conditions

  • Author

    Eveking, Hans ; Mai, Christoph

  • Author_Institution
    Inst. fur Datentech., Tech. Hochschule Darmstadt, Germany
  • fYear
    1990
  • fDate
    12-15 Mar 1990
  • Firstpage
    512
  • Lastpage
    517
  • Abstract
    Most timing-verifiers are analytical tools that determine, e.g., the delays on all paths, etc. This paper presents a completely different approach: timing-verification is performed by means of the formal transformation of CHDL descriptions. The principles of this procedure are presented and performance results of an implementation are given
  • Keywords
    circuit analysis computing; formal specification; theorem proving; CHDL descriptions; formal transformation; performance results; timing conditions; timing-verifiers; Assembly; Boolean algebra; Control systems; Delay; Formal verification; Hardware; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1990., EDAC. Proceedings of the European
  • Conference_Location
    Glasgow
  • Print_ISBN
    0-8186-2024-2
  • Type

    conf

  • DOI
    10.1109/EDAC.1990.136701
  • Filename
    136701
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2089359