Automatic generation of timing specifications for CMOS transistor subnetworks

A method for automatic and hierarchical generation of timing specifications for CMOS transistor subnetworks is presented. The result is delays and timing constraints relating the pins of the cells, which then can be handled at the gate/latch level. It can be used for verification, performance estimation and as timing data for cell libraries and multilevel simulators. The approach is fast since it is static and only the unique cell types need to be analysed. When used for verification by comparison this provides an important complement to functional verifiers