Title :
On applying circular self-test path (CSTP) technique to circuits
Author :
Njinda, Charles A. ; Srinivasan, Rajagopalan ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
It is pointed out that the use of a circular self-test path is an attractive built-in self-test technique due to the advantages of a single test session and ease of control. The authors present a procedure for selecting registers for a circular path so that each combinational block of the circuit is tested functionally exhaustively. High-level structural details like identity modes (I-modes) of the circuit are used to reduce the test time and area overhead at the expense of slightly more complex control. A mixed mode test strategy is suggested to improve the pattern coverage for the circuit. Analytical expressions are derived for estimating test time
Keywords :
built-in self test; combinatorial circuits; graph theory; logic testing; BIST; built-in self-test; circular self-test path; combinational block; fault coverage enhancement; graph partitioning; identity modes; mixed mode test strategy; pattern coverage; selection procedure; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design methodology; Equations; Kernel; Polynomials; Shift registers; Test pattern generators;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164115
