SystemC: from language to applications, from tools to methodologies

Summary form only given. This tutorial covers SystemC from more than just a language perspective. It starts with a brief survey of language features and capabilities, including some of the more recent developments such as the SystemC verification library. The usage of several of these language features, in particular for system-level modeling, design, verification and refinement are illustrated. We then address many interesting applications of SystemC drawn from a number of different industrial and academic research groups. Next, we talk about current tools available for design modeling, analysis and implementation with SystemC, covering the areas of co-simulation, synthesis, analysis, refinement, and testbenches, illustrating them with examples. Of course, tools are not enough; we also cover a number of methodology examples, in particular illustrating the use of SystemC in building complete design flows for complex SoC and system designs. This illustrates the linkage between SystemC and other design languages. We close with a few notes on possible future SystemC evolutions.