A high performance 30 V extended drain RESURF CMOS device for VLSI intelligent power applications

Author

Mei, P.C. ; Fujikura, K. ; Fawano, T. ; Malhi, S.

Author_Institution

Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1994

fDate

7-9 June 1994

Firstpage

81

Lastpage

82

Abstract

For the first time, high-performance, 30 V rated high voltage CMOS Lateral DMOS (LDMOS) devices for both high-side and low-side driver applications have been demonstrated. They utilize a simple twin-well single-tank, one level metal, 2.0 /spl mu/m CMOS process to optimize both N and P channel High Voltage (HV) devices simultaneously. This employs a self-aligned, Extended Drain (ED) Reduced surface Field (RESURF) approach to realize the best performance of both N and P channel devices. 1000 /spl Aring/ gate oxide has achieved the specific on-resistance (Rsp(on)) of 0.49 m/spl Omega/-cm/sup 2/ for N-ch (7.5 pm pitch) and 1.9 m/spl Omega/-cm/sup 2/ for P-ch (8.0 /spl mu/m pitch), and avalanche breakdown voltage of 36 V for N-ch and 44 V for P-ch devices respectively. This is the best 30 V rated HV-CMOS device performance level reported for RESURF LDMOS devices.<>

Keywords

CMOS integrated circuits; VLSI; driver circuits; impact ionisation; power integrated circuits; 2 micron; 36 V; 44 V; VLSI intelligent power applications; avalanche breakdown voltage; extended drain RESURF CMOS device; high-side driver; lateral DMOS devices; low-side driver; specific on-resistance; twin-well single-tank one level metal; Avalanche breakdown; Breakdown voltage; CMOS process; Implants; Instruments; Intelligent vehicles; Large scale integration; MOS devices; Power integrated circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324367

Filename

324367