DocumentCode
2089904
Title
Implementation of multiple-valued multiplier on GF(3m) using current mode CMOS
Author
Seong, Hyeon Kyeong ; Choi, Jai Seok ; Shin, Boo Sik ; Kim, Heung Soo
Author_Institution
Dept. of Comput. Sci. & Eng., Sangji Univ., South Korea
fYear
2000
fDate
2000
Firstpage
221
Lastpage
226
Abstract
The multiplication algorithm of two polynomials on finite fields GF(3m) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(33) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 μm standard CMOS device parameters, 20 μA unit current level and 3.3 V VDD voltage supply
Keywords
CMOS logic circuits; Galois fields; adders; current-mode logic; digital arithmetic; multiplying circuits; multivalued logic; multivalued logic circuits; 2 mum; 20 muA; 3-valued multiplier; 3.3 V; CMOS device parameters; GF(3) adders; GF(3) multipliers; GF(3m); Pspice simulations; current level; current mode CMOS; current-mode CMOS 3-valued multiplier; finite fields; multiple-valued multiplier; multiplication algorithm; polynomials; serial-in/parallel-out modular structures; Adders; Circuit simulation; Galois fields; Performance evaluation; Polynomials; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location
Portland, OR
ISSN
0195-623X
Print_ISBN
0-7695-0692-5
Type
conf
DOI
10.1109/ISMVL.2000.848623
Filename
848623
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