DocumentCode
2090031
Title
Boundary element method macromodels for 2-D hierarchical capacitance extraction
Author
Dengi, E. Aykut ; Rohrer, Ronald A.
Author_Institution
Motorola Inc., Austin, TX, USA
fYear
1998
fDate
19-19 June 1998
Firstpage
218
Lastpage
223
Abstract
A 2-D hierarchical field solution method was recently introduced for capacitance extraction for VLSI interconnect modeling. In this paper, we present several extensions to the method including a Boundary Element Method (BEM) formulation for creating macromodels, which provides a better trade-off between accuracy and efficiency, as well as parameterized elements, which allow the analysis of gridless designs with reasonable accuracy and a small library size.
Keywords
VLSI; boundary-elements methods; circuit analysis computing; integrated circuit interconnections; Boundary Element Method; VLSI interconnect modeling; capacitance extraction; gridless designs; macromodels; Boundary element methods; Capacitance; Conductors; Finite difference methods; Integrated circuit interconnections; Integrated circuit yield; Libraries; Permission; Runtime; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724470
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