DocumentCode :
2090107
Title :
A new pipelined array architecture for signed multiplication
Author :
Costa, Eduardo ; Bampi, Sergio ; Monteiro, José
Author_Institution :
UCPel, Pelotas, Brazil
fYear :
2003
fDate :
8-11 Sept. 2003
Firstpage :
65
Lastpage :
70
Abstract :
We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This architecture is extended for radix-2m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. We have implemented a pipelined version of the radix-4 architecture in order to reduce both the critical path and useless signal transitions that are propagated through the array. The performance of our pipelined architecture is compared with the pipelined modified Booth. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the modified Booth multiplier in the pipelined and non-pipelined approaches.
Keywords :
digital arithmetic; logic design; logic simulation; low-power electronics; multiplying circuits; pipeline arithmetic; array multiplier; modified Booth multiplier; partial line reduction; pipelined array architecture; power consumption reduction; radix-2m encoding; radix-4 architecture; signed multiplication; Computer architecture; Delay; Digital signal processing; Encoding; Energy consumption; Integrated circuit interconnections; Logic circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on
Print_ISBN :
0-7695-2009-X
Type :
conf
DOI :
10.1109/SBCCI.2003.1232808
Filename :
1232808
Link To Document :
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