DocumentCode
2090153
Title
CMOS Vt-control improvement through implant lateral scatter elimination
Author
Polishchuk, Igor ; Mathur, Nitish ; Sandstrom, Clifford ; Manos, Pete ; Pohland, Oliver
Author_Institution
Cypress Semicond., San Jose, CA, USA
fYear
2005
fDate
13-15 Sept. 2005
Firstpage
193
Lastpage
196
Abstract
This paper demonstrates that the threshold voltages of CMOS transistors can vary significantly depending on their proximity to well boundary. This well proximity effect (WPE) is caused by the well implant atoms that scatter laterally from the photo-resist mask. We examine the details of this scattering process, and describe several practical ways to eliminate the impact of well proximity effect.
Keywords
CMOS integrated circuits; integrated circuit manufacture; masks; photoresists; proximity effect (lithography); semiconductor device manufacture; transistors; voltage control; CMOS transistors; implant lateral scatter elimination; photo-resist mask; threshold voltages control; well proximity effect; CMOS process; Circuit simulation; Circuit synthesis; Implants; MOSFETs; Proximity effect; Resists; Scattering; Space technology; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on
Print_ISBN
0-7803-9143-8
Type
conf
DOI
10.1109/ISSM.2005.1513333
Filename
1513333
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