DocumentCode :
2090159
Title :
Towards a high-level synthesis of reconfigurable bit-serial architectures
Author :
Rettberg, Achim ; Dittmann, Florian ; Zanella, Mauro ; Lehmann, Thomas
Author_Institution :
Paderborn Univ., Germany
fYear :
2003
fDate :
8-11 Sept. 2003
Firstpage :
79
Lastpage :
84
Abstract :
This paper presents high-level synthesis methods for a fully reconfigurable self-timed synchronous bit-serial pipeline architecture. The idea is to distribute the central control unit. Local controls of the operators are realized through a one-shot implementation of the central control engine. Specialized routing components allow the reconfiguration of the implemented circuit with respect to rapid system prototyping. We describe several kinds of high-level synthesis approaches, especially the scheduling, which can be used for this type of architecture. This means we optimize specific characteristics, like loops, junctions and splitters, during the synthesis phase.
Keywords :
circuit optimisation; data flow graphs; high level synthesis; pipeline processing; processor scheduling; program control structures; reconfigurable architectures; circuit reconfiguration routing components; dataflow graph; high-level synthesis; junctions; loop optimization; pipeline architecture; reconfigurable bit-serial architectures; scheduling; self-timed synchronous architecture; splitters; Centralized control; Circuit synthesis; Delay; High level synthesis; Packaging; Particle separators; Pipelines; Prototypes; Signal synthesis; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on
Print_ISBN :
0-7695-2009-X
Type :
conf
DOI :
10.1109/SBCCI.2003.1232810
Filename :
1232810
Link To Document :
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