Title :
Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop
Author :
Uemura, Tetsuya ; Baba, Toshio
Author_Institution :
Fundamental Res. Labs., NEC Corp., Ibaraki, Japan
Abstract :
A novel T-gate consisting of multi-junction surface tunnel transistors (MJ-STTs) and hetero-junction FETs (HJFETs) were proposed and its operation was successfully confirmed by both simulation and experiment. The number of the devices required for their-gate can be drastically reduced due to a high functionality of the MJ-STT. Only three MJ-STTs and three HJFETs were required to fabricate the three-valued T-gate, whose number is less than one half of that of the conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic function. Furthermore, a multiple-valued data flip-flop (D-FF) circuit could be realized by only one T-gate
Keywords :
flip-flops; logic gates; multivalued logic circuits; flip-flop; logic function; multiple-junction surface tunnel transistors; multiple-valued T-gate; three-valued data flip-flop; Circuits; FETs; Flip-flops; Laboratories; Logic design; Logic devices; Logic functions; National electric code; Resonant tunneling devices; Voltage;
Conference_Titel :
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location :
Portland, OR
Print_ISBN :
0-7695-0692-5
DOI :
10.1109/ISMVL.2000.848636