DocumentCode :
2090186
Title :
A study on the ternary parallel circuit design with DCG properties based on the matrix equation
Author :
Byun, Gi-Noung ; Lee, Chol-U ; Park, Seung-Yong ; Kim, Heung-Soo
Author_Institution :
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
fYear :
2000
fDate :
2000
Firstpage :
311
Lastpage :
316
Abstract :
An efficient algorithm is proposed for ternary parallel circuit design satisfied with the given DCG relation. The proposed algorithm in this paper uses the matrix equation that can be induced from the relation of each node. In contrast to the conventional method, it has merit for circuit design process. From given DCG specification, following the proposed algorithm in this paper we can get the matrix equation easily. And then take the essential terms that satisfied with the DCG properties from the matrix equation. Using these terms, we can design the ternary parallel circuit. Also, we can apply this algorithm to DCG with any natural number´s length. This paper shows some design examples so that proves proposed algorithm´s generalization, compatibility and verification in ternary parallel circuit design
Keywords :
multivalued logic circuits; ternary logic; DCG properties; compatibility; matrix equation; ternary parallel circuit design; verification; Adders; Algorithm design and analysis; Arithmetic; Circuit synthesis; Combinational circuits; Delay; Equations; Integrated circuit interconnections; Integrated circuit technology; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location :
Portland, OR
ISSN :
0195-623X
Print_ISBN :
0-7695-0692-5
Type :
conf
DOI :
10.1109/ISMVL.2000.848637
Filename :
848637
Link To Document :
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