DocumentCode
2090226
Title
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS
Author
Leshner, Samuel ; Berezowski, Krzysztof ; Yao, Xiaoyin ; Chalivendra, Gayathri ; Patel, Saurabh ; Vrudhula, Sarma
Author_Institution
Arizona State Univ., Tempe, AZ, USA
fYear
2010
fDate
5-7 July 2010
Firstpage
210
Lastpage
215
Abstract
In this paper we describe the design, simulation, fabrication, and test of a 32-bit 2´s complement integer multiplier constructed from a combination of CMOS standard cells and threshold logic elements in a 65 nm low power process. As compared to a multiplier designed solely using CMOS standard cells, the threshold logic based multiplier is 1.23x smaller and consumes 1.41x less dynamic power and 2.5x less leakage power at the same process corner.
Keywords
CMOS logic circuits; logic design; logic testing; multiplying circuits; threshold logic; CMOS standard cells; threshold logic-based standard cell multiplier; CMOS integrated circuits; Clocks; Delay; Logic gates; Power demand; Radiation detectors; Testing; high performance; low leakage; low power; multiplier; standard cell; threshold logic;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location
Lixouri, Kefalonia
Print_ISBN
978-1-4244-7321-2
Type
conf
DOI
10.1109/ISVLSI.2010.32
Filename
5572773
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