FPGA-based hardware architecture for neural networks: binary radix vs. stochastic

Author

Nedjah, Nadia ; Mourelle, Lde.M.

Author_Institution

Dept. of de Syst. Eng. & Comput., State Univ. of Rio de Janeiro, Brazil

fYear

2003

fDate

8-11 Sept. 2003

Firstpage

111

Lastpage

116

Abstract

This paper is focused on the hardware implementation of neural networks. It describes the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs, while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time×area classic factor.

Keywords

digital arithmetic; feedforward neural nets; field programmable gate arrays; logic design; neural chips; stochastic programming; FPGA-based hardware architecture; binary input adders; binary input multipliers; binary radix arithmetic; feed-forward neural networks; fully connected artificial neural networks; input stochastic representation; neural network hardware implementation; stochastic arithmetic; stochastic computing; Neural network hardware; Neural networks; Stochastic processes; Stochastic systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on

Print_ISBN

0-7695-2009-X

Type

conf

DOI

10.1109/SBCCI.2003.1232815

Filename

1232815

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2090273