Title :
Scaling of tunnel oxide thickness for flash EEPROMs realizing stress-induced leakage current reduction
Author :
Watanabe, H. ; Aritome, S. ; Hemink, G.J. ; Maruyama, T. ; Shirota, R.
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
It has been reported that the tunnel oxide of flash E/sup 2/PROM is spoiled by the write/erase sequence of high-field stress and that leakage current (J/sub leak/)is induced at lower voltage, which deteriorates retention time and limits the tunnel oxide thickness of E/sup 2/PROM/sup ./ In order to scale down the tunnel oxide thickness, this paper proposes two new approaches to decrease the leakage current. One is the decreasing impurity concentration in the floating gate poly-Si. The other is to lower annealing process temperature after the floating gate formation. These reduction of J/sub leak/ is more remarkable as the tunnel oxide thickness is thinner. As a result, the tunnel oxide can be scaled down to 6 nm by decreasing gate poly-Si concentration to about 5/spl times/10/sup 19/cm/sup -3/ and lowering annealing temperature to less than 900/spl deg/C. These process will become the key technology to realize 64 Mb E/sup 2/PROM and beyond.<>
Keywords :
EPROM; MOS integrated circuits; VLSI; annealing; impurity distribution; integrated circuit technology; tunnelling; 6 nm; 64 Mbit; Si; annealing process temperature; flash EEPROMs; floating gate poly-Si; impurity concentration; oxide scaling; retention time; stress-induced leakage current reduction; tunnel oxide thickness; write/erase sequence; Annealing; Current measurement; EPROM; Impurities; Leakage current; Stress measurement; Temperature; Time measurement; Ultra large scale integration; Voltage;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324384
