Title :
Hardware implementation of “Supplementary symmetrical logic circuit structure” concepts
Author :
Olson, Dan ; Current, K. Wayne
Author_Institution :
EDO LLC, Big Bear City, CA, USA
Abstract :
A test chip was fabricated in a standard 1.2-micron CMOS technology using Supplementary Symmetrical Logic Circuit Structure (SUS-LOC) concepts. The test chip demonstrated several ternary logical functions as well as the flexibility of the SUS-LOC structure. Logic functionality and switching performance of the chip were simulated and verified experimentally. Simulated and experimental results are presented and discussed
Keywords :
CMOS logic circuits; multivalued logic circuits; ternary logic; CMOS technology; SUS-LOC; Supplementary Symmetrical Logic Circuit Structure; logic circuits; switching performance; ternary logical functions; CMOS logic circuits; CMOS technology; Circuit testing; FETs; Hardware; Lab-on-a-chip; Logic circuits; Read only memory; Switching circuits; Voltage;
Conference_Titel :
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location :
Portland, OR
Print_ISBN :
0-7695-0692-5
DOI :
10.1109/ISMVL.2000.848645
