A novel double well with buffer N/sup -/ and P/sup +/ gettering layers for suppression of soft error rate (DOWNSER)

Author

Komori, S. ; Yamashita, T. ; Kuroi, T. ; Inuishi, M. ; Tsubouchi, N.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1994

fDate

7-9 June 1994

Firstpage

41

Lastpage

42

Abstract

A novel double well with buffer n/sup -/ and gettering layers structure for strong suppression of SER (DOWNSER) is briefly presented in this paper. The mechanisms for reduction of SER have been investigated by experimental and simulation studies. The buffer n/sup -/ and the gettering layer in DOWNSER structure play the important role in cutting off the minority carrier generated from the incident alpha particle in the p-type region or the reverse biased junction.<>

Keywords

DRAM chips; alpha-particle effects; getters; integrated circuit technology; ion implantation; minority carriers; DOWNSER; DRAMs; buffer layers; double well; gettering layers; incident alpha particle; minority carrier; p-type region; reverse biased junction; soft error rate; Alpha particles; Boron; Current measurement; Dynamic voltage scaling; Error analysis; Gettering; Leakage current; Pollution measurement; Random access memory; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324387

Filename

324387