Title :
Design of a quaternary latch circuit using a binary CMOS RS latch
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
A new voltage-mode quaternary CMOS static latch circuit is presented that is built around a binary standard CMOS logic clocked RS latch circuit. Only devices available in a standard digital CMOS fabrication technology-enhancement-mode NMOS and PMOS transistors with single threshold voltage values-are used. No depletion-mode devices or special transistor threshold voltages are required. Its operation is experimentally verified. Typical and worst-case on-chip setup and hold times are simulated to be approximately 2.8 ns and 6.8 ns, respectively
Keywords :
CMOS logic circuits; logic design; multivalued logic circuits; CMOS static latch circuit; binary CMOS RS latch; quaternary latch circuit; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Fabrication; Latches; Logic devices; MOS devices; MOSFETs; Threshold voltage;
Conference_Titel :
Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on
Conference_Location :
Portland, OR
Print_ISBN :
0-7695-0692-5
DOI :
10.1109/ISMVL.2000.848646
