Title :
Enhancement of data retention time for giga-bit DRAMs using SIMOX technology
Author :
Tanigawa, T. ; Yoshino, A. ; Koga, H. ; Ohya, S.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
Abstract :
Both N-type and P-type stacked capacitor DRAM cells (L/sub g/=0.4 /spl mu/m) were fabricated on ultra-thin SIMOX substrates, and the data retention time was compared with that of a bulk counterpart. A data retention time of 550 sec (at 25/spl deg/C) could be achieves using ultra-thin SIMOX substrates, which is 6 times longer than that of the bulk memory cell. Specifically it is demonstrated that a P-type stacked capacitor cell on an ultrathin SIMOX substrate is very attractive and promising for future giga-bit DRAM cells.<>
Keywords :
DRAM chips; MOS integrated circuits; SIMOX; VLSI; cellular arrays; integrated circuit technology; 0.4 micron; 25 degC; 550 s; N-type cell; P-type cell; SIMOX technology; data retention time; giga-bit DRAMs; stacked capacitor DRAM cells; ultra-thin SIMOX substrates; Capacitance; Capacitors; Circuit testing; MOS devices; Random access memory; Semiconductor films; Silicon; Substrates; Ultra large scale integration; Voltage;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324389
