Algorithms and tools for network on chip based system design

Network on chip (NoC) is a new paradigm for designing core based system on chip. It supports a high degree of reusability and is scalable. In this paper, an efficient two-step genetic algorithm and the correlated software is described, mapping concurrent applications, which are described by a parameterized multi-task-graph, onto an NoC with a 2D mesh of switches as a communication backbone and populated with a known set of IP cores as computational resources. The algorithm proposes mathematical delay models and finds a good method of mapping vertices of the multi-task-graph to available cores so that every single task graph can meet its respective deadline. The correlated software has two separate tools. One can freely generate any NoC backbone and multi-task-graph for test. The other achieves the two-step genetic algorithm and can give the design result within one minute on a PC platform. It also provides facilities for viewing synthetic task graphs and the working progress of the genetic algorithm.