SoCIN: a parametric and scalable network-on-chip

Author

Zeferino, Cesar Albenes ; Susin, Altamiro Amadeu

Author_Institution

Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2003

fDate

8-11 Sept. 2003

Firstpage

169

Lastpage

174

Abstract

Networks-on-chip (NoCs) interconnection architectures, to be used in future billion-transistor systems-on-chip (SoCs), meet the major communication requirements of these systems, offering, at the same time, reusability, scalability and parallelism in communication. Furthermore, they cope with other issues like power constraints and clock distribution. Currently, there are a number of research works which explore different features of NoCs. In this paper, we present SoCIN, a scalable network based on a parametric router architecture to be used in the synthesis of customized low cost NoCs. The architecture of SoCIN and its router are described, and some synthesis results are presented.

Keywords

integrated circuit design; logic design; message passing; multiprocessor interconnection networks; network routing; packet switching; parallel architectures; system-on-chip; NoC interconnection architectures; SoC interconnection network; SoCIN; clock distribution; communication parallelism; embedded systems; message passing communication model; parametric network-on-chip; parametric router architecture; power constraints; reusability; router architecture; scalability; scalable NoC; switching networks; systems-on-chip; wormhole packet switched network; Clocks; Costs; Electronic mail; Integrated circuit interconnections; Network synthesis; Network-on-a-chip; Power system interconnection; Scalability; Space exploration; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on

Print_ISBN

0-7695-2009-X

Type

conf

DOI

10.1109/SBCCI.2003.1232824

Filename

1232824