Selective etching technology of in-situ P doped poly-Si (SEDOP) for high density DRAM capacitors

In order to keep a sufficient cell capacitance in a limited area, various kinds of three dimensional capacitor structures have been developed. However, fabrication procedure of those structures is very complicated, leading to a decrease in device yield and increase in manufacturing cost. Therefore, much effort has been focused on keeping the cell structure simple and manufacturable. Recently, surface enlargement methods such as hemispherical grained (HSG) Si and micro cavity have been developed, and by using these methods the surface could be enlarged as much as two times. However, these methods have a dielectric breakdown degradation characteristics and thickness dependence of NO capacitor dielectrics due to micro-grooves. Also the development of high dielectric films such as Ta/sub 2/O/sub 5/ and BaSrTiO/sub 3/ still have many problems in their application. In this work, we introduce a new technique called SEDOP (Selective Etching of in-situ P-Doped Poly-Si) for surface enlargement using large etch selectivity between phosphorus (P) in-situ doped poly-Si and undoped poly-Si. By using the SEDOP technique, a capacitor structure about 2 times larger in area and with a smooth surface can be formed with ease.<>