Reliability Analysis and Improvement in Nano Scale Design

According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. Several approaches for implementing the fault tolerance systems are already investigated. Most of these methods are applicable also in the case of high fault rates. Most protection methods are based on different redundancy methods which add extra detection and correction features to the design. We strongly believe that in future architectures it become more important assessing the fault tolerance techniques. Having an estimation of system fault tolerance can ensure critical applications working properly. In this work we propose a new method which checks reconfigurable architectures and during runtime finds violent spots in the design for probable transient and permanent failures. This approach is adjustable to either current FPGAs or future nano-architectures which are based on reconfigurability. We define a fault detection model for probable errors which uses an efficient algorithm that proves the fault tolerance in the reconfigurable architecture and computes a reliability factor for the architecture. This helps avoiding using the critical parts by future usages. Our method is applicable to different levels of granularity, such as gate level, logic block level, logic function level, unit level, etc. It is efficient and fast and can be simply integrated into the design flow.