Title :
0.1 /spl mu/m delta-doped MOSFET using post low-energy implanting selective epitaxy
Author :
Noda, K. ; Uchida, T. ; Tatsumi, Taizo ; Aoyama, T. ; Nakajima, K. ; Miyamoto, H. ; Hashimoto, T. ; Sasaki, I.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
Abstract :
Delta-doped NMOSFETs with 0.1 /spl mu/m gate length were fabricated by using Post Low-energy Implanting Selective Epitaxy (PLISE). Non-doped epitaxial channel layers were grown by UHV-CVD after BF/sub 2/ ion implanting at 10 keV. The delta-shaped doping configuration suppresses short-channel effects and reduces the junction capacitance. It allows the switching speed one and a half times faster than conventional approaches. The minimum gate delay is 7.2 ps at 2.5 V for an NMOS ring oscillator with a 10 /spl mu/m gate width and a 1 K/spl Omega/ load.<>
Keywords :
CMOS integrated circuits; MOS integrated circuits; doping profiles; insulated gate field effect transistors; integrated circuit technology; ion implantation; vapour phase epitaxial growth; 0.1 micron; 10 keV; BF/sub 2/ ion implant; NMOSFETs; PLISE; Si:BF/sub 2/; UHV-CVD; delta-doped MOSFET; junction capacitance; post low-energy implanting selective epitaxy; short-channel effects; switching speed; Capacitance; Doping; Epitaxial growth; Epitaxial layers; Impurities; Isolation technology; MOSFET circuits; Molecular beam epitaxial growth; National electric code; Threshold voltage;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324398
